FIG. 1 illustrates a memory cell array 10 of a conventional NAND-type non-volatile memory device. Referring to FIG. 1, the memory cell array 10 includes a bitline BLn, a plurality of wordlines WL0 through WLn, a string selection line SSL, a ground selection line GSL, a common source line CSL, a string selection transistor SST, a ground selection transistor GST, and multiple memory cells MC0 through MCn.
The string selection transistor SST is connected with the bitline BLn and is controlled by the string selection line SSL. The ground selection transistor GST is connected with the common source line CSL and is controlled via the ground selection line GSL.
The wordlines WL0 through WLn are respectively connected with gates of the memory cells MC0 through MCn and apply control voltages to the respective memory cells MC0 through MCn. The memory cells MC0 through MCn are connected in series between the string selection transistor SST and the ground selection transistor GST, forming a single string.
Usually, the non-volatile memory device like a flash memory can electrically read, program and erase data within the memory cells MC0 through MCn. The programming is an operation of recording data in each of the memory cells MC0 through MCn. To verify whether data has been normally programmed at each memory cell, a program verification operation is needed when each of the memory cells MC0 through MCn is programmed.
FIGS. 2A and 2B are diagrams for explaining voltages applied to the memory cells MC0 through MCn illustrated in FIG. 1 according to different operation modes. FIG. 3 is a graph illustrating the variation of threshold voltage of the memory cells MC0 through MCn illustrated in FIG. 1. FIG. 4A is a circuit diagram for conceptually explaining current change in the memory cells MC0 through MCn illustrated in FIG. 1 in different operation modes. FIG. 4B is a graph illustrating current changes in the memory cells MC0 through MCn illustrated in FIG. 1 in different operation modes.
Generally, in program verification, data can be read by applying a verification voltage Vvfy (i.e., Vvfy1, Vvfy2, or Vvfy3) to a selected memory cell (hereinafter, referred to as a selected cell) and detecting a current flowing in the selected cell. At this time, a high pass voltage Vread having a predetermined high level is applied to the other non-selected memory cells (hereinafter, referred to as non-selected cells). In a read operation, data can be read by applying a read voltage Vr1 or Vr2 to a selected cell and detecting a current flowing in the selected cell. At this time, the high voltage Vread having the predetermined voltage level is applied to the other non-selected cells.
Referring to FIGS. 2A and 2B, the memory cells MCi are sequentially programmed from the bottom cell to the top cell. FIG. 2A illustrates a voltage applied to the wordlines WL0 through WLn during the program verification after the selected cell, i.e., the bottom cell is programmed to “01”. FIG. 2B illustrates a voltage applied to the wordlines WL0 through WLn when the read operation is performed on the selected cell after the other non-selected cells are all programmed to “00”.
As illustrated in FIGS. 2A and 2B, when the non-selected cells are in an erase state “11” in the program verification and are programmed to “00” in the read operation, a threshold voltage of the non-selected cells in the program verification has a different level than that in the read operation. In other words, the non-selected cells have a lowest threshold voltage Vth0 among threshold voltages Vth0, Vth1, Vth2, and Vth3 during the program verification while they have a highest threshold voltage Vth3 during the read operation. Since the threshold voltage increases due to the change in data patterns of the non-selected cells, for example, from “11” to “00”, a channel resistance Rafter of the non-selected cells during the read operation is higher than a channel resistance Rinitial of the non-selected cells during the program verification. Accordingly, when the same high voltage Vread is applied to the non-selected cells during both of the program verification and the read operation, an on-cell current Icell′ or off-cell current Ioffcell′ flowing in the selected cell during the read operation is lower than an on-cell current Icell or off-cell current Ioffcell flowing in the selected cell during a program operation. Referring to FIG. 4B, the change in the off-cell current, i.e., the change from Ioffcell to Ioffcell′ is slight as is shown in graph (b), but the change in the on-cell current, i.e., the change from Icell to Icell′ can be big as is shown in graph (a).
In other words, when the selected cell is an on-cell, the current Icell′ flowing in the selected cell during the read operation can be significantly decreased from the current Icell flowing in the selected cell during the program verification. The on-cell indicates a memory cell, in which a threshold voltage is lowered (for example, to 0V or less) after electrons escape from a floating gate of a memory cell transistor, and is also referred to as an “erased cell”. Contrarily, the off-cell indicates the memory cell having a high threshold voltage after electrons are accumulated at the floating gate of the memory cell transistor and is also referred to as a “programmed cell”.
That the current Icell′ of the selected cell during the read operation is lower than the current Icell of the selected cell during the program verification means that the variation of threshold voltage of the selected cell during the read operation is different from that during the program verification. Referring to FIG. 3, right after data “01” is programmed to the selected cell, the variation of threshold voltage of the selected cell can be expressed in a curve L1. However, during the read operation on the selected cell, the channel resistance in the non-selected cells increases, and therefore, the variation of threshold voltage of the selected cell can change. At this time, the selected cell can have a wider variation of threshold voltage as expressed in a curve L2. As the variation of threshold voltage of the selected cell is widened, a read margin can be decreased.
The read margin is a gap between the threshold voltage (e.g., Vth1) and the read voltage (e.g., Vr1). The read margin has influence on detecting a memory cell as an on-cell (FIG. 4A) or an off-cell (FIG. 4B). However, when the threshold voltage of an off-cell (or a programmed cell) increases, a current flowing in the selected cell is decreased as illustrated in FIGS. 4A and 4B. As a result, the read margin is decreased and it can become difficult to discriminate on-cells from off-cells, potentially causing read errors.
As described above, the change in a data pattern of non-selected cells between the program verification and the read operation causes a channel resistance of the non-selected cells to change, and therefore, a current flowing in a selected cell is decreased. As a result, the read margin can be decreased. This phenomenon is a sort of back pattern dependency (BPD) effect where the selected cell is adversely affected by the non-selected cells.
Therefore, a non-volatile memory device for increasing the read margin of a memory cell by improving the BPD effect is desired.